1. Field of the Invention
The present invention relates to a method of manufacturing an interconnect. More particularly, the present invention relates to a method of manufacturing an interconnect in a high density integrated circuit device.
2. Description of the Related Art
Due to the increasingly high integration of ICs, chips simply cannot provide sufficient area for manufacturing interconnections. Therefore, in accord with the increased interconnects manufacturing requirements of miniaturized MOS transistors, it is increasingly necessary for IC manufacturing to adopt a design with more than two conductive layers. Commonly, the material of the conductive layer can be polysilicon or conductive metal. Generally, an inter-metal dielectric (IMD) layer is used to electrically isolate two adjacent conductive layers from each other. Moreover, a conductive layer used to electrically connect the two adjacent metal layers is called a via plug.
Typically, the parasitic capacitor effect easily happens between conductive wires. The parasitic capacitor effect induces resistor-capacitor time delay (RC time delay), so that the operation rate of the device is slow. Paracitic capacitance becomes increasingly serious as the size of the device reduces and integrated circuit device density becomes higher.